Smart Power Chips built with low/high voltage CMOS transistors are a significant part of the semiconductor technology for automotive applications. In automotive applications, the harsh environment demands robust protection against the threat of electrostatic discharge (ESD) or other transient pulses such as load dump. Automotive applications typically require a high human body model (HBM) stress level of protection at +/-2000 V. Unfortunately, many power MOSFET device designs are unable to meet this requirement.
One transistor structure used in power devices is the lateral DMOS (LDMOS). A prior art LDMOS is shown in FIG. 1. LDMOS 10 is located in substrate 12 and isolated from other structures (not shown) by field oxide region 14. The drain region 18 of LDMOS 10 is located in a high voltage tank region 16. The source region 22 is located in a p-well 20. The gate electrode 24 extends from the source region 22 over a thin gate oxide 26 and partially over a thicker oxide 28 located adjacent the drain region 18. Unfortunately, achieving acceptable levels of ESD protection with this LDMOS has been very difficult.
A typical circuit application for the LDMOS of FIG. 1 is shown in FIG. 2. A drain clamp (Zener diodes 30) and a gate clamp (Zener diode 32) are used to prevent the LDMOS 10 from entering bipolar breakdown when transient peaks occur at the drain 18 (from pad 34). This ensures that the LDMOS operates as a MOS device. FIG. 3 is a graph of drain current versus gate voltage for a 2400 micron device having a Vds of 20 V. As can be seen from curve 40, in normal operation, increasing the gate voltage above 6-8 volts causes a negligible increase in drain current. Since increasing the gate voltage above 6-8 volts requires extra Zener diodes (using more circuit area) and only a small increase in performance under normal operating conditions, the gate clamps are typically designed for the &lt;8 volt range.